The field of the invention is digital circuitry, and more specifically high precision input characteristic detection circuitry.
Detecting the phase of two inputs has presented unique challenges. In the past, analog circuits have been utilized to detect the phase of two inputs. Specifically, analog mixers have been used for phase detection. Unfortunately, analog mixers are more expensive and less convenient than digital circuits. In some applications, analog mixers are simply impractical.
One digital circuit solution has been to use exclusive-OR (xe2x80x9cXORxe2x80x9d) gates as phase detectors. If the two inputs are in phase, the resulting output of the XOR gate is known to be a low level output (i.e., zero volts). Likewise, if the two inputs are one-hundred eighty degrees out of phase, the resulting output of the XOR gate is known to be a high level output. Unfortunately, the transducer gain and offset of these results are sensitive to variations of temperature and supply voltage. Consequently, the precision and accuracy of a XOR gate phase detector is lacking.
What is needed is a digital circuit phase detector that is precise and accurate and is not substantially susceptible to errors such as those caused by temperature or supply voltage variations.
The present invention is an apparatus and method for detecting phase with precision. In an embodiment, the present invention utilizes a pair of logic gates applied to two inputs to allow the inputs to be processed by a differential amplifier to determine the phase of the inputs. The pair of logic gates are preferably XOR gates that perform exclusive OR operations on the two inputs. The first XOR gate performs an exclusive OR operation on a first input and a second input. The second XOR gate performs an exclusive OR operation on the first input and the inverted second input. The outputs of the second XOR gate and the first XOR gate are then subtracted to remove any common errors, such as those caused by temperature and input voltage variation.
The result of the subtraction is a phase indicating voltage that is without these common errors. From known voltage levels of the phase indicating voltage, the phase of the first input and the second input can be determined. The phase indicating voltage is at a minimum level when the first input and the second input are zero degrees out of phase (i.e., in phase), a medium level when the first input and the second input are ninety degrees out of phase and a maximum level when the first input and the second input are one-hundred eighty degrees out of phase. Accordingly, the phase detection is accomplished with high precision and accuracy.
An embodiment of the present invention utilizes two additional XOR gates. The third XOR gate is used to insert a propagation delay into the second input. This propagation delay is inserted to match the propagation delay caused by the fourth XOR gate which is used to invert the second input. The outputs of the third XOR gate and the fourth XOR gate are transmitted to the first XOR gate and the second XOR gate, respectively, for the exclusive OR operations with the first input. Use of four XOR gates is particularly convenient since XOR gates are often sold in packages of four gates.
In a preferred embodiment, the desired output of a phase detector is a low frequency average voltage resulting from lowpass filtering of the XOR gate output waveforms. This filtering may be inserted after each gate before a differential amplifier which may perform the subtracting of the waveforms or the differential amplifier may provide some or all of this filtering, either by its own characteristics or by appropriate feedback components, or the differential amplifier may be followed by a lowpass filter. In the embodiment shown, two capacitors are associated with the differential amplifier for this purpose.